Field of the Invention
This invention relates generally to data processing systems and more particularly to a data processing system having a multilevel memory including at least a first, small, high speed cache memory and one or more large, relatively slower main memories with an integrated control system therefor, having an improved channel to memory write system. The system of the present invention includes a swap buffer whereby data from the channel goes through the IPU to the swap buffer. Thereafter, the IPU is freed to do other work while the swap buffer obtains any needed half-word information from the main memory or from the cache and thereafter stores the new information in the main memory. This significantly increases overall system performance since the IPU can proceed with other work during the reading of information to complete storage requests which cross half-word boundaries.